One problem occurring in GaN based power components is dispersion. Dispersion is the change of the resistance of the channel (2DEG) after stressing the transistor, for example by applying a bias voltage to the drain, either in off-state, semi-on state or on-state, thereby creating an electric field transversal to the GaN based buffer layer, between the drain and the source-connected substrate. This buffer layer is one of the primary contributors for dispersion. The buffer typically has a high amount of point defects and threading dislocations due to heteroepitaxial growth on a foreign substrate (e.g. silicon), which could be potential charge trapping sites in the buffer. The buffer is also typically doped explicitly with dopants that can form either deep acceptors or donors, exacerbating the issue. Furthermore, the buffer typically is graded (for strain relief), creating a band offset between different parts of the buffer. There are built-in electric fields arising in the buffer due to the polarized nature of the material system. This can create potential wells, which can trap mobile charges in the buffer. All these contributions can lead to a high amount of charge trapping in the buffer when the buffer is stressed under a high potential. This charge trapping can then lead to the aforementioned channel (2DEG) dispersion.
Another problem is the so-called back-gating effect, which occurs when a GaN buffer is grown on a conductive carrier substrate, as is the case for GaN-on-Si. The conductive carrier can act as a backgate, meaning that it can control the electron concentration in the channel when a bias is applied to the carrier substrate. In particular, when the potential between the source (or drain) terminal and the substrate is negative, the channel will tend to deplete. This effect tends to cause issues when two transistors are co-integrated on the same substrate, typically referred as a “high side switch” and a “low side switch.” The two transistors need to share a common terminal at the substrate. A situation can therefore occur for which the carrier substrate is at a high negative potential compared to the channel of one of the transistors which is supposed to be in the on-state and creating unwanted depletion of its channel and thus increase the on-resistance of that transistor and decrease the efficiency of the system.
U.S. Patent App. Pub. No. 2010/0289067 is related to a device provided with a dispersion blocking layer between the channel layer and the buffer. A sheet or distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer. The negative charge distribution is obtained by polarization or doping and is confined to the interface between the channel layer and the blocking layer.
U.S. Patent App. Pub. No. 2013/0248874 is related to a nitride transistor configured to be able to sink electron and hole currents which are generated under avalanche operation of the device. It requires an energy minimum near the interface between the channel layer and backbarrier layer, which will attract holes during avalanching and is thus able to sink the hole current under this condition.